During the fabrication of integrated circuits on a silicon wafer, projecting features are produced, generally by etching. These are covered over the entire surface of the wafer with a coating of an external layer of a defined material. Next, a chemical-mechanical polishing operation is carried out so as to obtain a planar external surface on which the fabrication of the integrated circuits will continue.
Under particular polishing conditions, it is the polishing time which determines the position at the end of polishing of the polished external surface with respect to the subjacent projecting feature.
At the present time, this polishing time is determined, before carrying out the polishing of a batch of normally identical wafers, by experiments or by trial and error, by successively carrying out polishing operations and measurements of the remaining thickness of the covering material. This is what is proposed in particular in patent document EP 0,824,995.
Unfortunately, it turns out that a relatively high proportion of wafers have to be scrapped because the position of the polished external surface with respect to the subjacent projecting feature is outside preset limits.
Thus there is a need for a polishing process which would make it possible to improve the way the polished external surface is positioned with respect to the subjacent feature and consequently to reduce the proportion of wafers which do not satisfy the desired dimensional characteristics.